(1) Field of the Invention
The present invention relates to a driver circuit of an integrated circuit for driving light emitting elements such as light emitting diodes (LED) or fluorescent display elements, and more particularly to a driver circuit having a plurality of driving outputs.
(2) Description of the Prior Art
A conventional driver circuit of the kind to which the present invention relates is shown by a block diagram in FIG. 1. As shown therein, a 4-bit shift register 1 is provided with a DATA terminal for receiving a data signal (hereinafter referred to as "DATA signal") and a CLK terminal for receiving a clock signal (hereinafter referred to as "CLK signal"), and outputs an output signal of 4-bits in synchronization with the CLK signal. A 4-bit latch 2 is provided with a LAT terminal for receiving a latch signal (hereinafter referred to as "LAT signal"), and latches the 4-bit output signal outputted from the shift register 1 in response to the LAT signal. There are four AND gates 3 each having two input terminals to one of which a blank signal (hereinafter referred to as "BLK signal") is externally inputted as an external control signal and to the other of which the output signal from the latch 2 is inputted. The respective AND gates 3 perform logical AND operations on the two inputted signals and output their output signals from respective output terminals Q.sub.0 through Q.sub.3.
The operation of the conventional driver circuit described above is explained with reference to a timing chart shown in FIG. 2. The DATA signal serially inputted to the DATA terminal is loaded in or inputted to the 4-bit shift register 1 in response to the respective leading edges of the CLK signal, and is parallelly outputted from the 4-bit shift register 1. The output signals from the 4-bit shift register 1 are latched by the 4-bit latch 2 when the LAT signal is at a "High" level (hereinafter referred to as "H"), and are supplied to the AND gates 3. When the BLK signal is at a "low" level (hereinafter referred to as "L"), since the AND gates 3 are in their OFF state, the output signals from the output terminals Q.sub.0 -Q.sub.3 are always at "L". Contrary to the above, when the BLK signal turns to "H", since the AND gates 3 become ON, the output signals from the latch 2 are transferred to the output terminals Q.sub.0 -Q.sub.3 through the AND gates 3. In this case, when the BLK signal turns to "H", the output signals from the output terminals Q.sub.0 -Q.sub.3 change from "L" to "H" and, when the BLK signal turns to "L", the output signals from the output terminals Q.sub.0 -Q.sub.3 change from "H" to "L". Consequently, during the transient state of changes in the output signals from the output terminals Q.sub.0 -Q.sub.3, there flows a switching current which causes noise to be produced in signal lines. This switching current is proportional to the number of the outputs so that, where the number of the outputs is N, such current is N times the switching current of a single output.
In the conventional driver circuit, a large switching current to flow during the transient state of changes in the outputs from the output terminals Q.sub.0 -Q.sub.3 causes a voltage drop due to wiring resistance, so that the potentials of the power source voltage and the ground line which are inherently constant become unstable or unavoidably fluctuate. Here, since the BLK signal which is used such as for controlling the luminance of an LED or a fluorescent display element is supplied independently from or asynchronously with the CLK signal, there is a possibility for the potential fluctuations of the power source voltage and the ground line to overlap the leading edge timings of the CLK signal. The overlapping or coincidence of the potential fluctuations of the power source voltage and the ground line with the leading edge timings of the CLK signal leads to the problem that the data signal is erroneously loaded in or inputted to the shift register 1. This is a problem in the conventional driver circuit, which is to be solved by the invention.